1. Field of the Invention
This invention relates to semiconductor integrated circuits and, more particularly, to a semiconductor integrated circuit of the type in which A/D converters have an encoder section which outputs the result of a multiplication carried out with an analog value and a digital value using an output value of a selected decision circuit as a multiplier (or a multiplicand) and an input digital value as a multiplicand (or a multiplier).
2. Description of the Prior Art
FIG. 1 is a circuit diagram showing a conventional semiconductor integrated circuit as, for example, disclosed in U.S. patent application Ser. No. 07/111,047 of the present applicants, in which parallel comparison type A/D converters have an encoder section which outputs the result of a multiplication carried out using an output value of a decision circuit as a multiplier (or a multiplicand) and an input digital value as a multiplicand (or a multiplier).
In FIG. 1, reference numeral 1 designates a supply voltage terminal for supplying source voltage, to which are connected ladder registers 3,3 . . . for dividing the supply voltage into reference voltages for comparators 4,4 . . . , respective interim nodes of the ladder resistors 3,3 . . . being each connected to one input terminal of corresponding one of the comparators 4, 4 . . . . The comparators 4, 4 . . . each has another input terminal connected to an analog input terminal 2 which inputs analog values. Respective output terminals of the comparators 4,4 . . . are individually connected to a decision circuit 5 which outputs "1" according to analog value. Output terminals of the decision circuit 5 are connected to an input terminal of a control circuit 7 which carries out multiplication with respect to a digital value and an analog value input as objects for multiplication and outputs binary encoded multiplication results.
Digital input terminals for inputting digital values are connected to a control signal generating circuit 6 which generates a control signal according to each digital value. A signal line which inputs control signals generated by the control signal generating circuit 6 is connected to the control circuit 7. The control circuit 7 comprises a plurality of transfer gates and a plurality of OR gates. Its output terminals output aforesaid multiplication results.
Next, the manner of operation of the conventional semiconductor integrated circuit will be explained. For the sake of simplicity, it is assumed that the analog value has "2" of the decimal notation and the digital value has "3" of the decimal notation. The supply voltage applied to the supply voltage terminal 1 is divided by the ladder resistors 3, 3 . . . into reference voltages, which in turn are individually input to the comparators 4, 4 . . . . The comparators 4, 4 . . . compare the magnitude of such reference voltage and the analog value input to the analog input terminal 2, and if, for example, the analog value is greater than the reference voltage, they output "1" (High). The decision circuit 5 determines an analog value using the output of the comparators 4, 4 . . . and outputs "1" (High) according to the analog value. In this instance, the output signals A.sub.0, A.sub.1 . . . of the decision circuit 5 are (A.sub.3 =0, A.sub.2 =1, A.sub.1 =0, A.sub.0 =0) which represent "2" of decimal notation. The digital value is illustrative of an example of 2 bits, and assuming that the higher bit thereof is R.sub.1 and the lower bit is R.sub.0, higher bit R.sub.1, lower bit R.sub.0 =1 (High) because the digital value is in this example "3" of decimal notation. With respect to this digital value, the control signal generating circuit 6 generates five kinds of control signals (R.sub.0, R.sub.1, R.sub.1 R.sub.0, R.sub.1 R.sub.0, R.sub.1 +R.sub.0) as shown in FIG. 1, which control signals are given as gate signals of the transfer gates in the control circuit 7. In the instance of FIG. 1, control signals R.sub.0, R.sub.1, R.sub.1 R.sub.0 are 1 (High) with respect to the output signal A.sub.2 =1(High), and by the individual transfer gates being turned ON, output signals X.sub.0, X.sub.1 . . . of the control circuit 7 are (X.sub.3 =0, X.sub.2 =1, X.sub.1 =1, X.sub.0 =0), which represent "6" of the decimal notation. This value represents "2.times.3", a multiplication result with respect to the analog value and the digital value, and it can be fetched as an output of the control circuit 7. Where output A.sub.0 of the decision circuit 5 is 1 (High), all outputs of the control circuit 7 are 0 (Low) irrespective of the digital value, because the analog value is "0", and accordingly the multiplication result represents "0".
Conventional semiconductor integrated circuits of the type having a multiplication function employ the encoder section of a parallel comparison type A/D converter as above described. Therefore, an increase in the number of bits of analog inputs requires a greater area of wiring for output signaling by the decision circuit 5, and in addition it involves the problem that the control signal generating circuit 6 and the control circuit 7 become complicated, a greater circuit area being thus required.